Extra registers for qmp query. 

Stringified to allow for easy interpretation while debugging, and no ambiguity
while marshaling/parsing/unpacking.

Signed-off-by: Andres Lagar-Cavilla <andres@lagarcavilla.org>

Index: qemu/cpus.c
===================================================================
--- qemu.orig/cpus.c	2013-01-17 10:57:02.956404726 -0600
+++ qemu/cpus.c	2013-01-17 10:57:02.948404726 -0600
@@ -1204,6 +1204,7 @@
 {
     CpuInfoList *head = NULL, *cur_item = NULL;
     CPUArchState *env;
+    int r;
 
     for (env = first_cpu; env != NULL; env = env->next_cpu) {
         CPUState *cpu = ENV_GET_CPU(env);
@@ -1220,6 +1221,14 @@
 #if defined(TARGET_I386)
         info->value->has_pc = true;
         info->value->pc = env->eip + env->segs[R_CS].base;
+        r = asprintf(&info->value->cr0, TARGET_FMT_lx, env->cr[0]);
+        info->value->has_cr0 = r != -1;
+        r = asprintf(&info->value->cr3, TARGET_FMT_lx, env->cr[3]);
+        info->value->has_cr3 = r != -1;
+        r = asprintf(&info->value->cr4, TARGET_FMT_lx, env->cr[4]);
+        info->value->has_cr4 = r != -1;
+        r = asprintf(&info->value->efer, "%" PRIu64, env->efer);
+        info->value->has_efer = r != -1;
 #elif defined(TARGET_PPC)
         info->value->has_nip = true;
         info->value->nip = env->nip;
Index: qemu/qapi-schema.json
===================================================================
--- qemu.orig/qapi-schema.json	2013-01-17 10:57:02.956404726 -0600
+++ qemu/qapi-schema.json	2013-01-17 10:57:02.948404726 -0600
@@ -569,6 +569,15 @@
 #                If the target is Sparc, this is the PC component of the
 #                instruction pointer.
 #
+# @cr0: #optional If the target is i386 or x86_64, this is the CR1 register.
+#
+# @cr3: #optional If the target is i386 or x86_64, this is the CR3 register.
+#
+# @cr4: #optional If the target is i386 or x86_64, this is the CR4 register.
+#
+# @efer: #optional If the target is i386 or x86_64, this is the "efer"
+#                   (extended features) register.
+#
 # @nip: #optional If the target is PPC, the instruction pointer
 #
 # @npc: #optional If the target is Sparc, the NPC component of the instruction
@@ -585,6 +594,7 @@
 ##
 { 'type': 'CpuInfo',
   'data': {'CPU': 'int', 'current': 'bool', 'halted': 'bool', '*pc': 'int',
+           '*cr0': 'str', '*cr3': 'str', '*cr4': 'str', '*efer', 'str', 
            '*nip': 'int', '*npc': 'int', '*PC': 'int', 'thread_id': 'int'} }
 
 ##
